The present invention relates to a memory cell circuit for use in a random access memory (RAM), and more particularly, to such a cell circuit that is radiation hard.
A typical RAM memory cell circuit comprises two cross-coupled inverters, with each inverter comprising a pair of series coupled metal oxide semiconductor (MOS) transistors. Each pair has a series connected P-conductivity type channel (PMOS) transistor and a N-conductivity type channel (NMOS) transistor.
When the entire circuit is subject to transient radiation and has bias voltages applied, electron-hole pairs are generated in all the component materials, and a photocurrent flows between the circuit devices through the normally insulating layers and insulating substrates. In particular, it is recognized that the dominant failure mechanism of silicon-on-insulator (SOI) devices under transient radiation is photoconduction between silicon devices through the insulating substrate, e.g., sapphire. This effect can cause the charging or discharging of certain critical nodes such as gate electrodes of inverters thereby causing a change in logic state of the memory cell.
It is known from U.S. Pat. No. 4,063,225 to use a memory cell circuit having inverters with different output impedances to prevent WRITE during READ. However, sucn a circuit has been found to be not completely effective to prevent a change in logic state when the entire circuit is exposed to a high level of transient gamma or X-ray radiation.
It is therefore desirable to provide a memory cell circuit that enhances the stability of the latched logic state and resists a change in logic state even when the entire cell is subject to high intensity radiation.